Internal Project: C6
The C6 project (KO: Sept 2005) aims to build a new soft processor core and associated compiler tools for low-cost FPGAs. The primary motivation for the project is the need for a simple, yet powerful soft core that allows students to program FPGAs in embedded C in some of our labs. Rather than use an existing processor architecture, our independence of legacy issues allows us to rethink the entire C-to-FPGA concept. Instead of using a legacy core with some 90's or even 80's instruction set architecture (reflecting old technology), and retargeting a C compiler to this ISA, we start top down by choosing an ISA that is at (almost) the same high level as the intermediate RTL level within the compiler, with the VHDL core being thought of as a hardware interpreter of this ISA. Hence, both the compiler backend and the soft core are kept at a minimum. The effects of such a low-cost approach in terms of performance, footprint, etc., is one of the issues that are being studied in this project. The tool chain consists of the usual tools
- C compiler (the cross compiler, see above)
- Simulator (runs compiled code on host machine)
- Run-time system (libs + monitor on FPGA to upload and run)
- Debugger (runs code on FPGA under supervision)
- Soft core (the VHDL microcontroller that runs the code on FPGA)
Apart from the tool chain, there is a special interest in the model helicopter embedded control application that we use in one of our labs (see course in4073) so some of the guys are doing embedded systems research in a somewhat broader sense.
The C6 project is an ongoing research effort within the Embedded Software Laboratory.